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product overview s3c7515/p7515 1? 2 g electronics s m s u n g electronics s m s u n 1 product overview overview the s3c7515/p7515 single-chip cmos microcontroller has been designed for high-performance using samsung's newest 4 -bit cpu core, sam47 (samsung arrangeable microcontrollers). the S3P7515 is a microcontroller which has 16-kbyte one-time-programmable eprom but its functions are same to s3c7515. with its dtmf generator, 8-bit serial i/o interface, and ver satile 8-bit timer/counters, the s3c7515/p7515 offers an excel lent design solution for a wide variety of telecommunication applica tions. up to 55 pins of the 64-pin sdip or qfp package can be dedicated to i/o. seven vectored interrupts provide fast re sponse to internal and external events. in addit ion, the s3c7515/p7515 's advanced cmos technol ogy provides for low power consumption and a wide op erating voltage range. development support 0 the samsung microcontroller development system, smds, provides you with a complete pc-based develop - ment environment for s3c7 -series microcontrollers that is powerful, reliable, and portable. in addition to its window-based program development structure, the smds tool set includes versatile debugging, trace, instruction timing, and performance measurement applications. the samsung generalized assembler (sama) has been designed specifically for the smds environment and accepts assembly language sources in a variety of microprocessor formats. sama generates industry-standard hex files that also contain program control data for smds compatibility.
s3c7515/p7515 product overview 1 - 3 features summary memory ? 512 4-bit ram ? 16,384 8-bit rom 55 i/o pins ? input only: 4 pins ? i/o: 43 pins ? n-channel open-drain i/o: 8 pins memory-mapped i/o structure ? data memory bank 15 dtmf generator ? 16 dual-tone frequencies for tone dialing 8-bit basic timer ? 4 interval timer functions two 8-bit timer/counters ? programmable interval timer ? external event counter function ? timer/counters clock outputs to tclo0 and tclo1 pins external clock signal divider serial i/o interface clock generator watch timer ? time interval generation: 0.5 s, 3.9 ms at 32.768 khz ? 4 frequency outputs to the buz pin 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive mode ? lsb-first or msb-first transmission selectable bit sequential carrier ? supports 8-bit serial data transfer in arbitrary format interrupts ? 3 external interrupt vectors ? 4 internal interrupt vectors ? 2 quasi-interrupts power-down modes ? idle: only cpu clock stops ? stop: system clock stops oscillation sources ? crystal, ceramic for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 3.579545 mhz (typical) ? subsystem clock frequency: 32.768 khz (typical) ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.67, 1.33, 10.7 m s at 6.0 mhz ? 1.12, 2.23, 17.88 s at 3.579545 mhz ? 122 s at 32.768 khz operating temperature ? ? 40 c to 85 c operating voltage range ? 2.0 v to 5.5 v package types ? 64 sdip, 64 qfp
product overview s3c7515/p7515 1 - 4 function overview sam47 cpu all s3c7 -series microcontrollers have the advanced sam47 cpu core. the sam47 cpu can directly address up to 32 k bytes of program memory. the arithmetic logic unit (alu) performs 4-bit addition, subtraction, logical, and shift-and-rotate operations in one instruction cycle and most 8-bit arithmetic and logical operations in two cycles. cpu registers program counter a 14-bit program counter (pc) stores addresses for instruction fetches during program execution. usually, the pc is incremented by the number of bytes of the fetched instruction. the one instruction fetch that does not increment the pc is the 1-byte ref instruction which references instructions stored in a look-up table in the rom. whenever a reset operation or an interrupt occurs, bits pc13 through pc0 are set to the vector address. stack pointer an 8-bit stack pointer (sp) stores addresses for stack operations. the stack area is located in general-purpose data memory bank 0. the sp is 8-bit read/writeable and sp bit 0 must always be logic zero. during an interrupt or a subroutine call, the pc value and the psw are written to the stack area. when the service routine has completed, the values referenced by the stack pointer are restored. then, the next instruction is executed. the stack pointer can access the stack despite data memory access enable flag status. since the reset value of the stack pointer is not defined in firmware, you use program code to initialize the stack pointer to 00h. this sets the first register of the stack area to data memory location 0ffh. program memory in its standard configuration, the 16,384 8-bit rom is divided into four areas: ? 16-byte area for vector a ddresses ? 16-byte general-purpose area (0010 ?001fh) ? 96-byte instruction reference area ? 16,256-byte area for general-purpose program memory the vector address area is used mostly during reset operations and interrupts. these 16 bytes can alternately be used as general-purpose rom. the ref instruction references 2 x 1-byte or 2-byte instructions stored in reference area locations 0020h? 007fh. ref can also reference three-byte instructions such as jp or call. so that a ref instruction can reference these instructions, however, the jp or call must be shortened to a 2-byte format. to do this, jp or call is written to the reference area with the format tjp or tcall instead of the normal instruction name. unused locations in the ref instruction look-up area can be allocated to general-purpose use.
s3c7515/p7515 product overview 1 - 5 data memory overview the 512 4 bit data memory has four areas: ? 32 4-bit working register area ? 224 4 -bit general-purpose area in bank 0 which is also used as the stack area ? 256 4 -bit general-purpose ar ea in bank 1 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses the data memory area is also organized as three memory banks ? bank 0, bank 1, and bank 15. you use the select memory bank instruction (smb) to select one of the banks as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. after a hardware reset, data memory initialization values must be defined by program code. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1, or 15. when the emb flag is logic zero, only locations 00h?7fh of bank 0 and bank 15 can be accessed. when the emb flag is set to logic one, all three data memory banks can be accessed based on the current smb value. working registers the ram's working register area in data memory bank 0 is also divided into four register banks. each register bank has eight 4-bit registers. paired 4-bit registers are 8-bit addressable. register a can be used as a 4-bit accumulator and double register ea as an 8-bit extended accumulator; double registers wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use bank 0 for main programs and banks 1, 2, and 3 for interrupt service routines. bit sequential carrier the bit sequential carrier (bsc) mapped in data memory bank 15 is a 8-bit general register that you can manipulate using 1-, 4-, and 8-bit ram control instructions. using the bsc register, addresses and bit locations can be specified sequentially using 1-bit indirect address ing instructions. in this way, a program can generate 8-bit data output by moving the bit location sequentially, incrementing or decrementing the value of the l register. you can also use direct addressing to manipulate data in the bsc.
product overview s3c7515/p7515 1 - 6 control registers program status word the 8-bit program status word (psw) controls alu operations and instruction execution sequencing. it is also used to restore a program's execution environment when an interrupt has been serviced. program instructions can always address the psw regardless of the current value of data memory access enable flags. before an interrupt is processed, the psw is pushed onto the stack in data memory bank 0. when the routine is completed, psw values are restored. interrupt status flags (is1, is0), the enable memory bank and enable register bank flags (emb, erb), and the carry flag (c) are 1 - and 4-bit read/write o r 8-bit read-only addressable. skip condition flags (sc0?sc2) can be addressed using 8-bit read instructions only. select bank (sb) register two 4-bit locations called the sb register store address values used to access specific mem ory and register banks: the select memory bank register, smb, and the select register bank register, srb. 'smb n' instructions select a data memory bank (0, 1, or 15) and store the upper four bits of the 12-bit data memory address in the smb register. the 'srb n' instruction is used to select register bank 0, 1, 2, or 3, and to store the address data in the srb. the instructions 'push sb' and 'pop sb' move smb and srb values to and from the stack for interrupts and subroutines. clock circuits main system and subsystem oscillation circuits generate the internal clock signals for the cpu and peripheral hardware. the main system clock can use a crystal, ceramic, or rc oscillation source, or an externally-generated clock signal. the subsystem clock requires either a crystal oscillator or an external clock source. bit settings in the 4 -bit power control and system clock mode registers select the oscillation source, the cpu clock, and the clock used during power-down mode. the internal system clock signal (fxx) can be divided inter - nally to produce three cpu clock frequencies ? fxx/4, fxx/8, or fxx/64. interrupts interrupt requests may be generated internally by on-chip processes (intb, intt0, intt1, and ints) or externally by peripheral devices (int0, int1, and int4). there are two quasi-interrupts: int2 and intw. int2/ks0?ks7 detects rising/falling edges of incoming signals and intw detects time intervals of 0.5 sec onds or 3.91 milliseconds at the watch timer clock frequency of 32.768 khz. the following components support interrupt processing: ? interrupt enable flags ? interrupt request flags ? interrupt priority registers ? power-down termination circuit is1 is0 emb erb c sc2 sc1 sc0
s3c7515/p7515 product overview 1 - 7 power-down to reduce power consumption, there are two power-down modes: idle and stop. the idle instruction initiates idle mode and the stop instruction initiates stop mode. in idle mode, only the cpu clock stops while peripherals and the oscillation source continue to operate normally. stop mode effects only the main system clock ? a subsystem clock, if used, continues oscil lating. in stop mode, main system clock oscillation stops completely, halting all operations except for a few basic peripheral functions. reset or an interrupt (with the exceptions of int0) can be used to terminate either idle or stop mode. reset reset when a reset signal occurs during normal operation or during power-down mode, the cpu enters idle mode when the reset operation is initiated. when the standard oscillation stabilization interval (36.6 ms at 3.579545 mhz) has elapsed, normal cpu operation resumes. i/o ports the s3c7515/p7515 has 14 i/o ports. pin addresses for all i/o ports are mapped in bank 15 of the ram. there are 4 input pins, 43 configurable i/o pins, and 8 n-channel open-drain i/o pins, for a to tal of 55 i/o pins. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. timers and timer/counters the timer function has four main components: an 8-bit basic interval timer, two 8-bit timer/counters, and a watch timer. the 8-bit basic timer generates interrupt requests at precise intervals, based on the selected cpu clock fre quency. the programmable 8-bit timer/counters are used for external event counting, generation of arbitrary clock frequencies for output, and dividing external clock signals. the 8-bit timer/counter 0 generates a clock signal ( sck ) for the serial i/o interface. the watch timer has an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. its functions include real-time and watch-time measurement, and frequency outputs for buzzer sound. serial i/o interface the serial i/o interface supports the transmission or reception of 8 -bit serial data with an external device. the serial interface has the following functional components: ? 8-bit mode register ? clock selector circuit ? 8-bit buffer register ? 3-bit serial clock counter the serial i/o circuit can be set either to transmit-and-receive or to receive-only mode. msb-first or lsb-first transmis sion is also selectable. the serial interface operates with an internal or an external clock source, or using the clock signal generated by the 8-bit timer/counter 0. to modify transmission frequency, the appropriate bits in the serial i/o mode register (smod) must be manipulated.
product overview s3c7515/p7515 1 - 8 block diagram basic timer arithmetic and logic unit interrupt control block stack pointer program counter program status word p0.0 / sck p0.1 / so p0.2 / si p0.3 / btco 512 x 4-bit data memory watch timer 16 k byte program memory flags instruction decoder clock reset xin xtin xout xtout internal interrupts p8.0?p8.3 p4.0?p4.3 p5.0?p5.3 p6.0?p6.3 / ks0?ks3 p7.0?p7.3 / ks4?ks7 p9.0?p9.3 dtmf p10.0?p10.3 p11.0?p11.3 p12.0?p12.3 p13.0?p13.2 int0, int1, int2, int4 8-bit timer/ counter 0 i/o port 8 8-bit timer/ counter 1 i/o port 6 i/o port 7 i/o port 9 i/o port 10 i/o port 11 i/o port 12 i/o port 13 i/o port 0 serial i/o port p2.0 / tclo0 p2.1 / tclo1 p2.2 / clo p2.3 / buz i/o port 2 p3.0 / tcl0 p3.1 / tcl1 p3.2 p3.3 i/o port 3 i/o port 4 i/o port 5 dtmf generator p1.0 / int0 p1.1 / int1 p1.2 / int2 p1.3 / int4 input port 1 figure 1 -1 . s3c7515/p7515 simplified block diagram
s3c7515/p7515 product overview 1 - 9 pin assignments v ss p9.0 p9.1 p9.2 p9.3 p8.0 p8.1 p8.2 p8.3 p7.0 / ks4 p7.1 / ks5 p7.2 / ks6 p7.3 / ks7 p6.0 / ks0 p6.1 / ks1 p6.2 / ks2 p6.3 / ks3 xtout xtin xin xout reset p5.0 p5.1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0 / tcl0 p3.1 / tcl1 p1.3 / int4 p1.2 / int2 p1.1 / int1 p1.0 / int0 p13.2 p13.1 p13.0 p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p0.3 / btco p0.2 / si p0.1 / so p0.0 / sck p10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 p12.0 p3.3 p3.2 test dtmf v dd s3c7515 (64-sdip-750) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 figure 1 -2 . 64-sdip pin assignment diagrams
product overview s3c7515/p7515 1 - 10 32 31 30 29 28 27 26 25 24 23 22 21 20 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0 / tcl0 p3.1 / tcl1 v dd dtmf test p3.2 p3.3 p12.0 52 53 54 55 56 57 58 59 60 61 62 63 64 p8.0 p9.3 p9.2 p9.1 p9.0 v ss p1.3 / int4 p1.2 / int2 p1.1 / int1 p1.0 / int0 p13.2 p13.1 p13.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p8.1 p8.2 p8.3 p7.0 / ks4 p7.1 / ks5 p7.2 / ks6 p7.3 / ks7 p6.0 / ks0 p6.1 / ks1 p6.2 / ks2 p6.3 / ks3 xtout xtin xin xout reset p5.0 p5.1 p5.2 p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p0.3 / btco p0.2 / si p0.1 / so p0.0 / sck p10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 s3c7515 (64-qfp-1420f) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 figure 1 -2 . 64-qfp pin assignment diagrams (continued)
s3c7515/p7515 product overview 1 - 11 pin descriptions table 1 - 1. s3c7515/p7515 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-up resistors are software assignable; pull-up re sistors are automatically disabled for output pins. 15 (8) 14 (7) 13 (6) 12 (5) sck so si btco p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit and 4-bit read and test is possible. 4 -bit pull-up resistors are assignable by software to pins p1.0, p1.1, p1.2 and p1.3 . 1 (61) 2 (60) 3 (59) 4 (58) int0 int1 int2 int4 p2.0 p2.1 p2.2 p2.3 i/o same as port 0. 11 (4) 10 (3) 9 (2) 8 (1) tclo0 tclo1 clo buz p3.0 p3.1 p3.2 p3.3 i/o same as port 0. 34 (27) 33 (26) 29 (22) 28 (21) tcl0 tcl1 p4.0?p4.3 p5.0?p5.3 i/o 4-bit i/o ports. n-channel open-drain output up to 9 volts. 1-bit and 4-bit read/write and test is possible. ports 4 and 5 can be paired to support 8-bit data transfer. 8-bit unit pull-up resistors are assignable by mask option. 38?35 (31?28) 42?39 (35?32) ? p6.0?p6.3 p7.0?p7.3 i/o 4-bit i/o ports. 1-bit or 4-bit read/write and test is possible. port 6 pins are individually software configurable as input or output. 4-bit pull -up resistors are software assignable; pull-up re sistors are automati cally disabled for output pins (port 6 only). ports 6 and 7 can be paired to enable 8-bit data transfer. 51?48 (44?41) 55?52 (48?45) ks0?ks3 ks4?ks7 p8.0?p8.3 i/o same as port 0. 59?56 (52?49) ? p9.0?p9.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. 4-bit pull-up resistors are software assignable ; pull-up re sistors are automatically disabled for output pins. 63?60 (56?53) ? * parentheses indicate pin number for 64 qfp package.
product overview s3c7515/p7515 1 - 12 table 1 - 1. s3c7515/p7515 pin descriptions (continued) pin name pin type description number share pin p10.0?p10.3 p11.0?p11.3 i/o same as port 9. ports 10 and 11 can be paired to support 8-bit data transfer. 19?16 (12?9) 23?20 (16?13) ? p12.0?p12.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is possible. individual pins are software configurable as input or output. 4-bit pull-down resistors are software assignable; pull-down re sistors are automatically disabled for output pins. 27?24 (20?17) ? p13.0?p13.2 i/o 3-bit i/o port; characteristics are same as port 9. 7?5 (64?62) ? dtmf o dtmf output. 31 (24) ? sck i/o serial i/o interface clock signal 15 (8) p0.0 so i/o serial data output 14 (7) p0.1 si i/o serial data input 13 (6) p0.2 btco i/o basic timer clock output 12 (5) p0.3 int0, int1 i external interrupts. the triggering edge for int0 and int1 is selectable. int0 is synchronized to system clock. 4, 3 (61, 60) p1.0, p1.1 int2 i quasi-interrupt with detection of rising edges 2 (59) p1.2 int4 i external interrupt with detection of rising and falling edges. 1 (58) p1.3 tclo0 i/o timer/counter 0 clock output 11 (4) p2.0 tclo1 i/o timer/counter 1 clock output 10 (3) p2.1 clo i/o clock output 9 (2) p2.2 buz i/o 2 khz, 4 khz, 8 khz, or 16 khz frequency output at the watch timer clock frequency of 32.768 khz for buzzer sound 8 (1) p2.3 tcl0 i/o external clock input for timer/counter 0 34 (27) p3.0 tcl1 i/o external clock input for timer/counter 1 33 (26) p3.1 ks0?ks3 ks4?ks7 i/o quasi-interrupt inputs with falling edge detection 51?48 (44?41) 55?52 (48?45) p6.0?p6.3 p7.0?p7.3 * parentheses indicate pin number for 64 qfp package.
s3c7515/p7515 product overview 1 - 13 table 1 - 1. s3c7515/p7515 pin descriptions (concluded) pin name pin type description number share pin v dd ? power supply 32 (25) ? v ss ? ground 64 (57) ? reset i reset signal 43 (36) ? x in , x out ? crystal, ceramic, or r/c oscillator signal for main system clock. (for external clock input, use x in and input x in 's reverse phase to x out ) 45, 44 (38, 37) ? x t in , x t out ? crystal oscillator signal for subsystem clock. (for external clock input, use xt in and input xt in 's reverse phase to xt out ) 46, 47 (39, 40) ? nc ? no connection (must be connected to v ss ) 30 (23) ? * parentheses indicate pin number for 64 qfp package.
product overview s3c7515/p7515 1 - 14 table 1 - 2. overview of s3c7515/p7515 pin data pin names share pins i/o type reset value circuit type p0.0?p0.3 sck , so, si, btco i/o input d-4 p1.0? p1.3 int0, int1, int2 , int4 i input a- 3 p2.0?p2.3 tclo0, tclo1, clo, buz i/o input d-2 p3.0?p3.1 tcl0, tcl1 i/o input d-4 p3.2?p3.3 ? i/o input d-2 p4.0?p4.3 p5.0?p5.3 ? i/o (note) e-6 p6.0?p6.3 p7.0?p7.3 ks0?ks3 ks4?ks7 i/o input d-4 p8.0?p8.3 ? i/o input d-2 p9.0?p9.3 ? i/o input d-2 p10.0?p10.3 p11.0?p11.3 ? i/o input d-2 p12.0?p12.3 ? i/o input d-6 p13.0?p13.2 ? i/o input d-2 dtmf ? o high impedence g-6 x in , x out xt in , xt out ? ? ? ? reset ? i ? b nc ? ? ? ? v dd , v ss ? ? ? ? note : when pull-up resistors are provided: high level when pull-up resistors are not provided: high impedence
s3c7515/p7515 product overview 1 - 15 pin circuit diagrams p - channel in n - channel v dd figure 1 -3 . pin circuit type a in p - channel pull-up resistor enable v dd pull-up resistor schmitt trigger figure 1 -4 . pin circuit type a- 3 schmitt trigger v dd pull-up resistor in figure 1 -5 . pin circuit type b schmitt trigger in figure 1 -6 . pin circuit type b-4
product overview s3c7515/p7515 1 - 16 v dd p-channel data output disable n-channel out figure 1 -7 . pin circuit type c p-channel pull-up enable data output disable i/o v dd circuit type c figure 1 -8 . pin circuit type d-2 p-channel pull-up enable data output disable schmitt triger i/o v dd circuit type c figure 1 -9 . pin circuit type d-4 data output disable i/o circuit type c pull-down enable n-channel figure 1 -10 . pin circuit type d-6
s3c7515/p7515 product overview 1 - 17 data output disable v dd pull-up resistor (mask option) i/o n-channel figure 1 -11. pin circuit type e-6 output disable dtmf out + - figure 1-12. pin circuit type g-2
s3c7515/p7515 electrical data 14- 1 14 electrical data in this section, information on s3c7515 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? absolute maxi mum ratings ? d.c. electrical characteristics ? system clock oscillator characteristics ? i/o capacitance ? a.c. electrical characteristics ? operating voltage range miscellaneous timing waveforms ? a.c timing measurement point ? clock timing measurement at x in and x out ? tcl timing ? input timing for reset ? input timing for external interrupts ? serial data transfer timing stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initia ted by reset ? stop mode release timing when initiated by an interrupt request
electrical data s3c7515/p7515 14- 2 table 14- 1 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? -0.3 to 6.5 v input voltage v i1 all i/o ports - 0.3 to v dd + 0.3 v output voltage v o ? - 0.3 to v dd + 0.3 v output current high i oh one i/o port active - 15 ma all i/o ports active - 30 output current low i ol one i/o port active + 30 (peak value) ma + 15 * all i/o ports, total + 100 (peak value) + 60 * operating temperature t a ? - 40 to + 85 c storage temperature t stg ? - 65 to + 150 c * the values for output current low ( i ol ) are calculated as peak value duty . table 14- 2 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units input high voltage v ih1 all input pins except those specified below for v ih2 - v ih4 0.7 v dd ? v dd v v ih2 ports 0, 1, 3, 6, 7, and reset 0.8 v dd v dd v ih3 ports 4 and 5 with pull-up resistors assigned 0.7 v dd v dd ports 4 and 5 are open-drain 0.7 v dd v dd v ih4 x in ,x out and xt in v dd - 0.1 v dd input low voltage v il1 all input pins except those specified below for v il2 - v il3 ? ? 0.3 v dd v v il2 ports 0, 1, 3, 6, 7, and reset 0.2 v dd v il3 x in ,x out and xt in 0.1
s3c7515/p7515 electrical data 14- 3 table 14- 2 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units output high voltage v oh i oh = - 1 ma ports except 1,4 and 5 v dd - 1.0 ? ? v output low voltage v ol1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 4,5 only ? ? 2 v v dd = 2.0 to 5.5 v i ol = 1.6ma ? 0.4 v v ol2 v dd = 4.5 v to 5.5 v i ol = 4ma all out ports except ports 4,5 2 v v dd = 2.0 to 5.5 v i ol = 1.6ma 0.4 v input high leakage current i lih1 v i = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v i = v dd x in , x out and xt in 20 input low leakage current i lil1 v i = 0 v all input pins except below and reset ? ? - 3 m a i lil2 v i = 0 v x in , x out and xt in - 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? - 3 pull-up resistor r l1 v dd = 5 v ; v i = 0 v except reset and p4.5 25 47 100 k w v dd = 3 v 50 95 200 r l2 v o =v dd -2v, v dd =5v ports 4 and 5 only 15 47 70 v dd =3v 10 45 60 r l3 v dd = 5 v ; v i = 0 v; reset 100 220 400 v dd = 3 v 200 450 800 pull-down resistor r l4 v dd = 5 v ; v i = v dd ; port 12 25 47 100 v dd = 3 v 50 95 200
electrical data s3c7515/p7515 14- 4 table 14- 2 . d.c. electrical characteristics (con cluded ) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units supply current (1) i dd1 (dtmf on) run mode; vdd=5.0v 10% 3.58mhz crystal oscillator; c1=c2=22pf ? 2.2 5.0 ma v dd = 3 v 10% 1.2 3.0 i dd2 run mode; v dd =5.0v 10% 6.0 mhz 3.9 8.0 ( dtmf off) crystal oscillator; c1=c2=22pf 3.58 mhz 2.0 4.0 v dd = 3 v 10% 6.0 mhz 1.8 4.0 3.58 mhz 0.8 2.3 i dd3 idle mode; v dd = 5 v 10% 6.0 mhz 1.3 2.5 3.58 mhz 0.6 1.8 v dd = 3 v 10% 6.0 mhz 0.5 1.5 3.58 mhz 0.4 1.0 i dd4 run mode; v dd =3.0v 10% 32 khz crystal oscillator 15 .3 30 m a i dd5 idle mode; v dd =3.0v 10% 32 khz crystal oscillator 6.4 15 i dd6 stop mode; v dd = 5 .0v 10% 2.5 5 v dd =3.0v 10% 0.5 3 row tone level v row v dd = 5 v 10% v dd = 3 v 10% v dd = 2 v rl = 5k w -16 -14 -11 dbv ratio of column to row tone db cr v dd = 5 v 10% v dd = 3 v 10% v dd = 2 v rl = 5k w 1 2 3 db distortion (dual tone) thd v dd = 5 v 10% v dd = 3 v 10% v dd = 2 v rl = 5k w , 1mhz band ? ? 5 % notes: 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resistors. 2. for d.c. electrical values , the power control register (pcon) must be set to 0011b.
s3c7515/p7515 electrical data 14- 5 table 14- 3 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v) oscillato r clock configuration parameter test condition min typ max units ceramic oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5 v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5 v 0.4 ? 4.2 stabilization time (2) v dd = 3v ? ? 4 ms crystal oscillator xin xout c1 c2 oscillation frequency (1) v dd = 2.7 v to 5.5v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5v 0.4 ? 4.2 stabilization time (2) v dd = 3 v ? ? 10 ms external clock xin xout x in input frequency (1) v dd = 2.7 v to 5.5v 0.4 ? 6.0 mhz v dd = 2.0 v to 5.5v 0.4 ? 4.2 x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
electrical data s3c7515/p7515 14- 6 table 14- 4 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xtin xtout c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd =2.7v to 5.5v ? 1.0 2 s v dd =2.0v to 5.5v ? ? 10 s external clock xtin xtout xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xh , t xl ) ? 5 ? 15 s notes: 1. oscillation frequency a nd xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabil ization after a power-on occurs or when stop mode is terminated. table 14- 5 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf
s3c7515/p7515 electrical data 14- 7 table 14- 6 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units instruction cycle time (1) t cy v dd = 2.7 v to 5.5 v 0. 67 ? 64 s v dd = 2.0 v to 5 .5 v 0.95 tcl0, tcl1 input frequency f ti0, f ti1 v dd = 2.7 v to 5.5 v 0 ? 1.5 mhz v dd = 2.0 v to 5 .5 v 1 m hz tcl0, tcl1 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? s v dd = 2.0 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 670 v dd = 2.0 v to 5 .5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v external sck source 335 ? ? ns internal sck source t kcy ? 2 50 v dd = 2.0 v to 5 .5 v external sck source 1600 internal sck source t kcy ? 2 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 2.0 v to 5.5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 2.0 v to 5.5 v external sck source 600 internal sck source 500
electrical data s3c7515/p7515 14- 8 table 14- 6 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units output delay for sck to so t kso (note) v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 2.0 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 , int1, int2, int4, ks0?ks7 10 ? ? s reset input low width t rsl input 10 ? ? s note: r (1 k w ) and c (100 pf) are the load resistance and load capacitance of the so output line . cpu clock = oscillator frequency x 1/n (n = 4, 8, 64) supply voltage (v) 1.05 m hz 1.5 mhz 15.625 khz cpu clock 1 2 3 4 5 6 7 6 mhz 4.2 mhz 2.7 v main osc. freq. (divided by 4) figure 14- 1 . standard operating voltage range
s3c7515/p7515 electrical data 14- 9 table 14- 7 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 1.5 ? 5.5 v data retention supply current i dddr v dddr = 1.5 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? ms notes : 1. during osc illator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
electrical data s3c7515/p7515 14- 10 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 14- 2 . stop mode release timing when initiated by reset reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 14- 3 . stop mode release timing when initiated by interrupt request
s3c7515/p7515 electrical data 14- 11 measurement points 0.8 vdd 0.8 vdd 0.2 vdd 0.2 vdd figure 14- 4 . a.c. timing measurement points (except for x in and xt in ) x in t xl t xh 1 / f x v dd ? 0.1 v 0.1 v figure 14- 5 . clock timing measurement at x in (xt in ) tcl t til t tih 1 / f ti 0.8 vdd 0.2 vdd figure 14-6. tcl 0/1 timing
electrical data s3c7515/p7515 14- 12 reset t rsl 0.2 vdd figure 14-7. input timing for reset reset signal int0, 1, 2, 4 ks0 to ks7 t intl t inth 0.2 vdd 0.8 vdd figure 14-8. input timing for external interrupts and quasi-interrupts
s3c7515/p7515 electrical data 14- 13 sck t kl t kh t kcy input data output data si so t sik t ksi t kso 0.2 vdd 0.8 vdd 0.2 vdd 0.8 vdd figure 14-9. serial data transfer timing
electrical data s3c7515/p7515 14- 14 characteristic curves note the characteristic values shown in the following graphs are based on actual test measurements. they do not, however, represent guaranteed operating values. 5.0 i dd (ma) (t a = 25 c) 4.0 3.0 1.0 0.8 0.6 0.4 0.2 1 2 3 4 fx (mhz) 0 5 i dd 1 (@3.5 v, fx/4) 2.0 7.0 6.0 i dd 1 (@5.5 v, fx/4) i dd 3 (@3.5 v, fx/4) i dd 3 (@5.5 v, fx/4) i dd 1 (@5.5 v, fx/64) figure 14- 1 0. i dd vs. frequency
s3c7515/p7515 electrical data 14- 15 5.0 4.0 3.0 2.0 i dd (ma) (t a = 25 c, fx = 4.2 mhz) 1.2 1.0 0.8 0.6 0.4 0.2 3 4 5 6 v dd (v) 0 i dd 3 (idle mode) * i dd 5 (stop mode) ** i dd 2 (operating mode, dtmf off) * 6.0 i dd 1 (operating mode, dtmf on) * i dd 3 (idle mode) ** i dd 2 (operating mode, dtmf off) ** i dd 1 (operating mode, dtmf on) ** * fx/64 ** fx/4 figure 14- 1 1. i dd vs. v dd
electrical data s3c7515/p7515 14- 16 10 0 i ol (ma) 0.5 v ol (v) 1.0 1.5 2.0 (t a = 25 c, p0, 2, 3, 6 ? 13) 20 30 40 50 60 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.0 v 4.5 v figure 14- 1 2. i ol vs. v ol (p0, 2, 3, and 6?13) ?5 0 i oh (ma) 0.5 v oh (v) 1.0 1.5 2.0 (t a = 25 c, p0, 2, 3, 6 ? 13) ?10 ?15 ?20 ?25 ?30 2.5 3.0 3.5 4.0 5.0 5.5 6.0 6.0 v 4.5 v 4.5 figure 14- 1 3. i oh vs. v oh (p0, 2, 3, and 6?13)
s3c7515/p7515 electrical data 14- 17 10 0 i ol (ma) 0.5 v ol (v) 1.0 1.5 2.0 (t a = 25 c, p4, 5) 20 30 40 50 60 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.0 v 4.5 v figure 14- 1 4. i ol vs. v ol (p4 and 5) frequency (mhz) 2.0 1.0 0.8 0.4 0.2 0 0 50 200 400 800 600 10 100 300 500 700 (t a = 25 c, v dd = 5 v) 4.0 3.0 900 1000 figure 14- 16 . frequency vs. resistor
s3c7515/p7515 mechanical data 15- 1 15 mechanical data this section contains the following information about the device package: ? package dimensions in millimeters ? pad diagram ? pad/pin coordinate data table 64-qfp-1420a 2.45 max 1.00 typ 0.40 0.1 25.00 0.3 20.00 typ 14.00 typ 19.00 0.3 1.20 0.2 0.10 + 0.1 ? 0.05 0.15 + 0.1 ? 0.05 note : typical dimensions are in millimeters. figure 15- 1 . 64-qfp-1420a package dimensions
mechanical data s3c7515/p7515 15- 2 6 4 - q f p - 1 4 2 0 c 3 . 0 0 m a x 0 . 8 0 0 . 2 0 . 1 5 0 . 1 n o t e : t y p i c a l d i m e n s i o n s a r e i n m i l l i m e t e r s . 1 7 . 2 0 0 . 3 1 4 . 0 0 2 3 . 2 0 0 . 3 2 0 . 0 0 0 . 4 0 0 . 1 ( 1 . 0 0 ) 6 4 ( 1 . 0 0 ) # 1 1 . 0 0 0 . 8 0 0 . 2 2 . 6 5 0 . 1 0 . 1 5 0 . 1 5 + 0 . 1 ? 0 . 0 5 figure 15- 2 64-qfp-1420c package dimensions
s3c7515/p7515 mechanical data 15- 3 64-sdip-750 57.80 0.2 17.00 0.2 1.00 0.1 0.51 min 1.778 typ 0.45 0.1 5.08 max 3.30 0.3 0 ~ 15 19.05 typ 0.25 +0.1 ? 0.05 note : typical dimensions are in millimeters. figure 15- 3 . 64-sdip-750 package dimensions
s3c7515/p7515 s3p75 15 otp 16- 1 1 6 S3P7515 otp overview the S3P7515 single-chip cmos microcontroller is the otp (one time programmable) version of the s3c7515 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the S3P7515 is fully compatible with the s3c7515, both in function and in pin configuration. because of its simple programming requirements, the S3P7515 is ideal for use as an evaluation chip for the s3c7515. vss / vss p9.0 p9.1 p9.2 p9.3 p8.0 p8.1 p8.2 p8.3 p7.0 / ks4 p7.1 / ks5 p7.2 / ks6 p7.3 / ks7 p6.0 / ks0 p6.1 / ks1 p6.2 / ks2 p6.3 / ks3 xtout xtin xin xout reset / reset reset p5.0 p5.1 p5.2 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0 / tcl0 p3.1 / tcl1 p1.3 / int4 p1.2 / int2 p1.1 / int1 p1.0 / int0 p13.2 p13.1 p13.0 p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p0.3 / btco p0.2 / si p0.1 / so p0.0 / sck p10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 p12.0 sdat / p3.3 sclk / p3.2 vpp / test dtmf vdd / vdd S3P7515 (64-sdip-750) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 note : the bolds indicate a otp pin name. figure 16-1. S3P7515 pin assignments (64-sdip)
S3P7515 otp s3c7515/p7515 16- 2 p5.3 p4.0 p4.1 p4.2 p4.3 p3.0 / tcl0 p3.1 / tcl1 v dd / vdd dtmf test / vpp p3.2 / sclk p3.3 / sdat p12.0 p8.0 p9.3 p9.2 p9.1 p9.0 vss / v ss p1.3 / int4 p1.2 / int2 p1.1 / int1 p1.0 / int0 p13.2 p13.1 p13.0 p2.3 / buz p2.2 / clo p2.1 / tclo1 p2.0 / tclo0 p0.3 / btco p0.2 / si p0.1 / so p0.0 / sck p10.3 p10.2 p10.1 p10.0 p11.3 p11.2 p11.1 p11.0 p12.3 p12.2 p12.1 S3P7515 (64-qfp-1420f) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p8.1 p8.2 p8.3 p7.0 / ks4 p7.1 / ks5 p7.2 / ks6 p7.3 / ks7 p6.0 / ks0 p6.1 / ks1 p6.2 / ks2 p6.3 / ks3 xtout xtin xin xout reset / reset reset p5.0 p5.1 p5.2 note : the bolds indicate a otp pin name. figure 16-2. S3P7515 pin assignments (64-qfp)
s3c7515/p7515 s3p75 15 otp 16- 3 table 16-1. descriptions of pins used to read/write the eprom pin name during programming pin no. i/o function sdat 28 (21) i/o serial data pin. output port when reading and input port when writing. can be assigned as a input / push-pull output port. sclk 29 (22) i serial clock pin. input only pin. vpp(test) 30 (23) i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset 43 (36) i chip initialization v dd / v ss 32 (25) / 64 (57) i logic power supply pin. v dd should be tied to +5 v during programming. note: parentheses indicate pin number for 64 qfp package. table 16-2. comparison of S3P7515 and s3c7515 features characteristic S3P7515 s3c7515 program memory 16 k byte eprom 2 k byte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test)=12.5v pin configuration 64sdip / qfp 64sdip / qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the S3P7515, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 14-3 below. table 16-3. operating mode selection criteria v dd vpp (test) reg/ mem mem address (a15-a0) r/ w w mode 5 v 5 v 0 0000h 1 eprom read 12.5v 0 0000h 0 eprom program 12.5v 0 0000h 1 eprom verify 12.5v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3P7515 otp s3c7515/p7515 16- 4 table 16-4. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v) parameter symbol conditions min typ max units supply current (1 ,2 ) i dd1 (dtmf on) run mode; v dd =5.0v 10% 3.58mhz crystal oscillator; c1=c2=22pf ? 2.2 5.0 ma v dd = 3 v 10% 1.2 3.0 i dd2 run mode; v dd =5.0v 10% 6.0 mhz 3.9 8.0 ( dtmf off) crystal oscillator; c1=c2=22pf 3.58 mhz 2.0 4.0 v dd = 3 v 10% 6.0 mhz 1.8 4.0 3.58 mhz 0.8 2.3 i dd3 idle mode; v dd = 5 v 10% 6.0 mhz 1.3 2.5 3.58 mhz 0.6 1.8 v dd = 3 v 10% 6.0 mhz 0.5 1.5 3.58 mhz 0.4 1.0 i dd4 run mode; v dd =3.0v 10% 32 khz crystal oscillator 15 .3 30 m a i dd5 idle mode; v dd =3.0v 10% 32 khz crystal oscillator 6.4 15 i dd6 stop mode; v dd = 5 .0v 10% 2.5 5 v dd =3.0v 10% 0.5 3 notes: 1. d.c. electrical values for supply current (i dd1 to i dd3 ) do not include current drawn through internal pull-up resistors. 2. for d.c. electrical values , the power control register (pcon) must be set to 0011b.
s3c7515/p7515 s3p75 15 otp 16- 5 cpu clock = oscillator frequency x 1/n (n = 4, 8, 64) supply voltage (v) 1.05 m hz 1.5 mhz 15.625 khz cpu clock 1 2 3 4 5 6 7 6 mhz 4.2 mhz 2.7 v main osc. freq. (divided by 4) figure 16-3. standard operating voltage range
S3P7515 otp s3c7515/p7515 16- 6 start address= first location v dd =5v, v pp =12.5v x = 0 program one 1ms pulse increment x x = 10 verify 1 byte last address v dd = v pp = 5 v compare all byte device passed increment address verify byte device failed pass fail no fail yes fail no figure 16-4. otp programming algorithm

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